1. Field of the Invention
The present disclosure generally relates to the fabrication of integrated circuits, and, more particularly, to various methods of forming gate structures by performing a gate-cut-last process and the resulting structures.
2. Description of the Related Art
In integrated circuits fabricated using metal-oxide-semiconductor (MOS) technology, field effect transistors (FETs) (both NMOS and PMOS transistors) are provided that are typically operated in a switching mode. That is, these transistor devices exhibit a highly conductive state (on-state) and a high impedance state (off-state). FETs may take a variety of forms and configurations. For example, among other configurations, FETs may be either so-called planar FET devices or three-dimensional (3D) devices, such as FinFET devices.
A field effect transistor (FET), irrespective of whether an NMOS transistor or a PMOS transistor is considered, and irrespective of whether it is a planar or 3D FinFET device, typically comprises doped source and drain regions that are formed in a semiconducting substrate that are separated by a channel region. A gate insulation layer is positioned above the channel region and a conductive gate electrode is positioned above the gate insulation layer. The gate insulation layer and the gate electrode may sometimes be referred to as the gate structure for the device. By applying an appropriate voltage to the gate electrode, the channel region becomes conductive and current is allowed to flow from the source region to the drain region. In a planar FET device, the gate structure is formed above a substantially planar upper surface of the substrate. In some cases, one or more epitaxial growth processes are performed to form epi semiconductor material in recesses formed in the source/drain regions of the planar FET device. In some cases, the epi material may be formed in the source/drain regions without forming any recesses in the substrate for a planar FET device.
In general, one commonly employed technique for forming gate structures for either planar or 3D devices involves forming a line-type gate electrode structure above a layer of insulating material that is formed above an active region defined in a semiconductor substrate. Typically, the line-type gate electrode structures are formed by depositing or thermally growing a layer of gate insulation material, e.g., silicon dioxide, on the spaced-apart active regions that are separated by isolation material, blanket-depositing a layer of gate electrode material, e.g., polysilicon or amorphous silicon, on the gate insulation layer and blanket-depositing a gate cap material layer on the layer of gate electrode material. Thereafter, gate electrodes for the devices are typically formed by patterning at least the gate cap layer and the layer of gate electrode material to define long parallel line-type structures, i.e., gate electrode structures, that extend across multiple spaced-apart active regions and the isolation regions formed in the substrate between such spaced-apart active regions. These long, line-type gate electrode structures are initially patterned so as to have the desired critical dimension, i.e., the dimension of gate electrode corresponding to the “gate length” (or direction of current travel) of the finished device. At some point later in the process flow, these long, line-type gate electrode structures are subsequently “cut” by performing an etching process to define the gate electrodes having the desired length in the “gate-width” direction of the transistor device. This results in substantially rectangular-shaped gate structures (when viewed from above) having the desired dimensions in the gate-length and gate-width directions.
After the gate electrodes are patterned, a sidewall spacer is typically formed around the perimeter of the substantially rectangular-shaped gate structure, i.e., the spacer is formed adjacent all four side sidewalls (two sidewalls and two end surfaces) of each of the patterned gate electrodes. In some cases, a thin liner layer may be formed on the gate structure prior to forming the sidewall spacer. The sidewall spacer, in combination with the gate cap layer, function to protect the gate electrode structure in subsequent processing operations. In the case where transistor devices are manufactured using so-called gate-first processing techniques, the gate structures (gate electrode plus the gate insulation layer) formed as described above are final gate structures for the device. In the situation where transistor devices are manufactured using so-called gate-last processing techniques, the gate structures (gate electrode and gate insulation layer) formed as described above are sacrificial in nature and will be subsequently removed (after several process operations are performed) and replaced with a final gate structure for the device. In the gate-last processing technique, the final gate structure typically includes one or more layers of high-k (k greater than 10) insulating material and one or more layers of metal that constitute at least part of the conductive gate electrode of the final gate structure.
Unfortunately, as device dimensions have decreased and packing densities have increased, it is more likely that, when epi semiconductor material is formed in the source/drain regions of the planar or 3D transistor device, some of the epi material may undesirably form on the end surfaces of the polysilicon/amorphous silicon gate electrode. This may occur for several reasons. The extent and amount of undesirable epi semiconductor material formation will vary depending upon the particular application and the quality of the manufacturing processes used to manufacture the device. In a worst case scenario, this undesirable epi semiconductor material may form around the entire end surface of a particular gate electrode so as to effectively from a conductive “bridge” between one or both of the source/drain regions and the gate electrode. In another example, such undesirable epi semiconductor material may span the space between the opposing end surfaces of two spaced-apart gate electrode structures, wherein the epi material may form on one or both of the spaced-apart gate structures. As a result of such undesirable and unpredictable epi formation, the resulting semiconductor devices and the integrated circuits including such devices may completely fail or operate at less than acceptable performance levels. One solution to remedy the potential formation of such undesirable epi material would be to simply make the end-to-end spacing between two adjacent gate structures and the pitch between such adjacent gate structures large enough so extra thick spacers could be formed around the gate structures. However, such a “solution” would lead to reduced packing densities, which is counter to the ongoing trend in the industry now and for the foreseeable future.
FIGS. 1A-1E simplistically depict one illustrative prior art process for forming gate structures and the problems that may be encountered when forming epi material using such a process flow. In general, the drawings contain a plan view and various cross-sectional views that are taken where indicated in the plan view. The plan view in FIG. 1A depicts two spaced-apart active regions 102A, 102B that are separated by isolation material 104, and two illustrative gate structures (depicted in dashed lines in FIG. 1A since they are not yet formed at this point in the process flow). With continuing reference to the plan view in FIG. 1A, the view “X-X” is a cross-sectional view taken along the “gate-length” or current transport direction for the finished transistor device formed above the active region 102A, i.e., a cross-sectional view through the gate structures. The view “Y-Y” is a cross-sectional view that is taken through the long axis of the gate structures formed above both of the active regions 102A, 102B, i.e., a cross-sectional view through the gate structures in the gate-width direction of the transistor devices.
FIG. 1A depicts the product 100 at a point in fabrication wherein the spaced-apart active regions 102A, 102B were defined in the substrate 102 by the formation of isolation structures 104. The isolation structures 104 may be formed using well-known techniques. The overall size of the active regions 102A, 102B may vary depending upon the particular application.
FIG. 1B depicts the product 100 after a layer of gate insulation material 105, a layer of gate electrode material 106 and a layer of gate cap material 107 were blanket-deposited above the product 100. In the plan view in FIG. 1B, the outlines of the active regions 102A, 102B are depicted in dashed lines for reference purposes.
FIG. 1C depicts the product 100 after one or more etching processes were performed through one or more patterned etch masks, e.g., patterned layers of photoresist material, to pattern the various layers of material and thereby define a gate stack 101X. These etching processes define gate structures 101X having a gate electrode 106 with substantially vertically oriented sidewalls 106S (view X-X) and tapered end surfaces 106E (view Y-Y). The tapered end surfaces 106E are formed due to the relatively close spacing between adjacent end surfaces 106E, and the resulting etch-loading effects. The patterning of the gate stacks 101X is typically accomplished by performing a first etching process to define long line-shaped features that may span across several active regions, having a width 101L corresponding to the gate-length or “critical dimension” of the finished transistor device. Then, at some point later in the process flow, a so-called “gate-cut” process is performed to cut the line-shaped features into individual gate structures, each of which may span one or more active regions. The second gate-cut process is reflected by the formation of the space 111 between the two separate gate structures positioned above the active regions 102A-B, respectively. That is, using prior art methods, the end face surfaces 106E are patterned after patterning the side surfaces 106S of what will ultimately become the substantially rectangular-shaped gate structures (when viewed from above) having the desired dimensions in the gate-length and gate-width directions.
As shown in FIG. 1D, after the gate structures 101X are completely patterned, a sidewall spacer 109 is formed along the sidewalls 106S and the end surfaces 106E of the gate structures 101X. The sidewall spacer 109 may be formed by depositing a layer of spacer material, e.g., silicon nitride, and thereafter performing an anisotropic etching process on the layer of spacer material so as to result in the spacers 109 depicted in the FIG. 1D. The base thickness or width of the spacers 109 may vary depending upon the particular application, e.g., 5-15 nm. During the formation of the spacers 109, the gate insulation layer 105 serves as an etch mask to protect the surface of the active regions 102A, 102B. As shown in FIG. 1D, after the spacers 109 are formed, an etching process may be performed to remove the exposed portions of the gate insulation layer 105. Unfortunately, due to the tapering of the end surfaces 106E, the sidewall spacer 109 may not cover or encapsulate the entire end surface 106E of the gate electrode structure 106. That is, portions of the gate electrode 106 may be exposed after the spacers 109 are formed, as simplistically depicted in the dashed-line regions 113.
Next, as shown in FIG. 1E, an epi semiconductor material 115, e.g., silicon, silicon/germanium, is formed on the exposed portions of active regions 102A, 102B positioned outside of the spacers 109. Unfortunately, due to the existence of the exposed portions of the gate electrode 106, i.e., the regions 113 not covered by the sidewall spacers 109, undesirable epi material 115A may grow from the exposed portions of the gate electrode 106. In one scenario, as depicted in FIG. 1E, this undesirable epi material 115A may actually merge or contact a similar region of undesired epi material 115A formed on an adjacent transistor. Obviously, such a “bridging” situation may lead to reduced device performance and/or complete device failure.
The present disclosure is directed to various methods of forming gate structures by performing a gate-cut-last process and the resulting structures that may avoid, or at least reduce, the effects of one or more of the problems identified above.